Delay timing circuit

ABSTRACT

A timer apparatus includes a timer circuit utilizing the charging and discharging of a capacitor. The timer circuit comprises a timing capacitor adapted to charge in the direction for cutting-off a transistor at the setting time, a switch adapted to apply the voltage in the direction for discharging of said capacitor, and a transistor adapted to be turned conductive after a given time from the commencement of discharging. Said timer has excellent temperature and voltage characteristics without employing a Zener diode and FET, is hardly affected by the D.C. current amplification factor of said transistor and the open-circuit voltage of a relay and can determine a set time to be several seconds through dozens of minutes.

United States Patent 1191 Takagi et a1. May 7, 1974' [54] DELAY TIMINGCIRCUIT 3,600,610 8/1971 Kelsch 307 293 1 1 Katsuyuki Magi, 91w;3:352:22? 1133; 111;'?.::i::::.... ...::::"33%72ZZ Miwa Minokamo, bothof Japan U 2,923,963 2/1960 Chesson etall... 307/293 x Assignee: KaishaTo ai NO'ITIS X 3,059,129 10/1962 Tottlngham 307/293 X se'sakushoNlshlkasugal'gun 3,215,856 11/1965 M0561 et al... 307/293 Pref Japan3,633,050 1/1972 Zavac 307/293 [22] Filed: Mar. 30, 1972 P E S l D M n Jrimary xaminertan ey i er, r. [21] Appl' 239572 Attorney, Agent,orFirmwoodhams, Blanchard and Flynn [30] Foreign Application PriorityData Mar. 31, 1971 Japan 46-19153 ABSTRACT I A timer apparatus includesa timer circuit utilizing the [52] U.S. CI. 307/293, 317/ 141 S, 328/131charging and discharging of'a capacitor. The timer cir- [51 1 Int. Cl. tcuit omprises a capacitor adapted to charge in Field of Search 307/293,10 LS; 3l5/82, he direction for cutting-off a transistor at the setting315/77, 83; 317/141 S; 328/l29l3 time, a switch adapted to apply thevoltage in the direction for discharging of said capacitor, and atransis- 1 References Cited tor adapted to be turned conductive after agiven time UNITED STATES PATENTS from the commencement of discharging.Said timer 3,274,434 9/1966 Miller 315/82 has excellent temperature andvoltage characteristics 3,287,608 11/1966 Pokrant 1 317/142 1 a t u p yg a Zener diode and is hardly 3,389,296 6/1968 0211111111.... 315/82affected by the DC current amplification factor of 3,40 .3 2 8 Ec3l7/14| S j said transistor and-the open-circuit voltage of a relayRoberts t t and can determine a et to be everal econds 3,544,838 12/1970Carruth et al. 315/83 through dozens of i V 3,546,527 12/1970 Chunn etal. 315/82 3,582,715 6/1971 Traina 307/293 6 Claims, 4 Drawing FiguresDELAY TIMING CIRCUIT The present invention relates to a timer device andmore particularly to a timer device capable of determining a set time tobe several seconds through dozens of minutes by utilizing semiconductorcircuits.

Various types of prior art timers are known; for instance, athermal-responsive type (bimetal) timer, a motor type timer, or anelectronic (a semiconductor) type timer, etc In a timer for anautomobile which utilizes a DC. source'as its power source (such as atimer for a defogger, a timer for an automatic choke, a warning timerfor seatbelts, 'an off-delay timer for headlights and a timer forturning out a headlight after a given time of period has passed since anautomobile stops), the voltage of its power source varies, so that amotor type timer cannot be utilized and a thermal-responsive timer hasbeen used in most cases. Such conventional thermal-responsive typetimers are subject to the influence of the ambient temperature andtherefore apt to be inaccurate in setting a predetermined time, and itthis transistor is increased and it becomes necessary to provide with atransistor having such a large collector loss as can counterbalancetherewith, which would raise the cost. The fact that the transistor fordriving a relay passes slowly through the active region means that atfirst on the exciting coil of the relay is applied a full sourcevoltage, then such voltage gradually decreases to an open-circuitvoltage near the end of the set time. Therefore, when the transistor isin the active region, a sufficient exciting voltage is not appliedthereto thus, even with only a slight vibration, the relay may possiblybe opened, although the set predetermined time has not yet passed.-

The present invention has been made to overcome the above-mentioneddisadvantages. lt is therefore an object of the present invention toprovide a timer which has excellent temperature and voltagecharacteristics without employing such expensive semiconductor elementsas a Zener diode or a field-effect transistor and which is not affectedby the DC. current amplification factor of the transistors employed andwhich is the further has a disadvantage that a set time for a subsequentoperation is by far shortened due to the thermal inertia in cases wheresequential operation is effected.

In recent years, as the cost of the semiconductor with the trip level ofa Schmidt circuit or the threshold voltage between the base and theemitter ofa transistor itself, or upon comparison of the chargingvoltage applied from a power source to a timing capacitor through atiming resistor, with the trip level of a Schmidt circuit or thethreshold voltage between the base and the emitter of a transistor.However, the above-mentioned circuits are easily affected by thevariation of the source voltage and therefore necessitate employment ofa Zener diode to improve the voltage characteristic. Furthermore, wheresuch a timer is constructed to have a relatively long set time, thevariation of the trip level of a Schmidt circuit or the capacitorvoltage in the vicinity of the threshold voltage ofa transistor ismadeless severe, so that the circuit is not only apt to be affected by noisebut is sensitive to variations in ambient temperature and sourcevoltage, so as to be liable to produce an error in the set time.Further, in

some such circuit structures, wherein the transistor for driving relayspasses slowly through the active region in response to the slackvariation of the capacitor voltage,

' age of the relay or the DC. current amplification factor of atransistor not only has fluctuation in the measured value, but alsovaries in the value with variation in theenvironmental temperature,thereby increasing the temperature-dependency of the set time andreducing the accuracy thereof. Another disadvantage, due to the factthat the transistor for driving a relay passes slowly through the activeregion is that the collector loss of open-voltage of the relay andcapable of obtaining a set time of several seconds through dozens ofminutes.

Another object of the present invention is to provide a timer which isadapted to expend no electric power when operates as a timer, due to thecomplete interruption of the circuits and loads from power sources, andto produce no erroneous operation due to external noise even with a highimpedance circuit.

A further object of the present invention is to provide a timer whichemploys no elements other than the fundamental circuit elements forvoltage regulation and temperature compensation as a timer, and which iscapable of, in its performance, being fully stable against the variationof power supply voltage or ambient temperature in normal use and whichcan be manufactured at reasonable cost.

'The above, as well as still further objects, features and advantages ofthe present invention will become apparent upon consideration of thefollowing detailed description of several specific embodiments thereof,especially when taken in conjunction with the accompanying drawings,wherein:

' According to the present invention, there is provided a timer deviceincluding a timer circuit utilizing the charging and discharging of acapacitor, comprising a timing capacitor adapted to charge in thedirection for cutting-off a transistor at the time of setting; a switchadapted to apply a voltage in the direction for discharging the chargedelectric charge of said capacitor to cause such discharge; and saidtransistor adapted to be turned conductive after a predetermined periodof time has passed from the commencement of discharging, thereby todetermine a set time.

H0. 1 is a circuit diagram of one preferred embodiment of the presentinvention; I

FIGS. 2 through 4 are circuit diagramsof modified embodiments inaccordance with the present invention.

Referring now to the drawings, and more particularly to FIG. 1 thereof,there is illustrated a circuit of one embodiment. of the invention. Edesignates a DC. power source, SW a switch for setting and resetting, R,a charging resistor, one terminal of which is connected with a settingcontact P of the setting-resetting switch SW and the other terminal ofwhich is connected with a positive electrode or a timing capacitor C. R:is a reone terminal of which resistor is connected with a +3 I powersupply line and the other of which is connected with the junction of thenegative electrode of said timing capacitor C and a base of a firststage transistor Tn. R, is a collector resistor one terminal of which isconnected with the +B power source line and the other terminal of whichis connected with both a collector of the first stage transistor Tr, anda base of a second stage transistor Tr The emitters of the first and thesecond stage transistors Tr, andTr are connected to the negativeterminal of the power source E. R .is a base resistor, one terminal ofwhich is connected with said contact P, of the setting-resetting switchSW and theother terminal of which connects with the base of the secondstage transistor Tr Y is a relay for controlling a load current andincludes a coil Y,, one terminal of which is connected with the +8 powersupply line and the other terminal'of which connects with a collector ofthe second stage transistor Tr Relay y further includes a contact y, oneterminal of which is connected with a positive terminal of the powersupply E and the other terminal of which connects with the +B,powersupply line. D, is'a diode, for preventing a counter electro-motiveforce connected in parallel with the coil Y, of said relay Y. Concerningthe setting-resetting switch SW, a setting contact P is connected withthe positive terminal of the power supply E and a setting contact P5connects with the +8 power supply line, respectively, while a resettingcontact P, is connected with the base of the second stage transistorTrand another resetting contact P connects with the negative terminal ofthe power supply E, respectively. L is a load having a terminalconnected with the negative terminal of the power supply and anotherterminal connected with the +B power supply line.

The operation of the above-mentioned circuit will be explained in detailas follows. When the movable contact PM the setting-resetting switch SWis turned to the setting side contacts P,, P and P,,, the positiveterminal of the power supply E is connected with the.

. +B power supply line of said circuit. Therefore, the

feed to the load L is commenced and the charging current flows from thecontact P, through the charging resistor R,, timing capacitor C and thebase-emitter of the first stage transistor Tr, to charge the timingcapacitor C it up to the following voltage.

where V0 is the charging voltage of a timing capacitor C,.Vd thebase-emitter forward voltage of the transistor Tr, and E the powersupply voltage.

Since there is determined and accordingly said transistor Tr, is madeconductive to excite the coil Y, of the relay Y and close the contact y.Then, when the setting-resetting switch SW is released, the movablecontact P of said switch SW is returned to a neutral position and the'switch side of the charging resistor R, is disconnected from the powersupply E, so that the positive electrode side of the timing capacitor Cismaintained nearly at the earth potential. At the same time, thevoltage at thebase of the first stage transistor Tr, becomes Vo and saidtransistor Tr, is cut off, while the second stage transistor Tr,

maintains the conductive condition by the current flowing through thecollector resistor R even if no current flowsthrough the base resistor Rthus maintaining the relay Y closed. I On the other hand, upon releasingthe settingresetting switch SW, the base potential of the first stagesecond stage transistor Tr, through the base resistor R transistor Tr,,which is reversely biased to *Vo, increases towards the power supplyvoltage by the current supplied from the +8 power supply line throughtiming resistor R Thus, when thebase potential becomes thebase-emitterthreshold voltage Vd of the transistor Tr,, said first stage transistor,Tr, becomes conductive, and the collector of said transistor Tr,becomes nearly the earth potential. Resultantly, the second stagetransistor Tr, is cut off, and the relay Y is made'open to interrupt thecurrent to the load L, thereby terminating'one delay operation. When thetimer operation comes to an end, the contact y: of the relay Y is openedandboth the load L and the timer circuit itself will be completelyseparated from the power supply E, as the movable contact 'P of thesetting resetting switch SW stands in the neutral'position.

.After the setting-resetting switch SW has been thrown into the settingside, if it isrequired'for some reasons to reset before the set time hasbeen passed, the movable contact P of the setting-resetting switch SW isthrown into the resetting side contacts P, and P to where. t

a R /R, +R b 12 /12, +R, +R, Vd, the base-emitter threshold voltage ofthe first stage transistor Tr, Vd the base-emittervoltage of the secondstage transistor Tl'g in the conductive condition E power supply voltageWhen the temperature coefficient of the timing resistor R and the timingcapacitor C is equal to zero, a

pression it will be seen that the set time will hardly be affected bythe variation of the power supply voltage and the environmentaltemperature. In the worst case when the power supply voltage varies fromto V, and the environmental temperature varies in all the domain between30C through 70C, only 4% of difference-will be produced. Therefore,without employing such expensive semiconductor elements as a 'Zenerdiode for compensating the voltage characteristic, a thermistor forcompensating the temperature characteristic and a semiconductorvaristor, a very stable set time in practical use will be obtained and atimer with high accuracy will be provided. W v 7 It is usual that theconventional silicon transistor has a base-emitter reverse withstandvoltage (reverse breakdown voltage) of 5 7V. In the circuit of theabove-mentioned embodiment of the present invention, in case the powersupply voltage is 12V, R, and R are so determined that the constanta=0.4, the-first stage transistor Tr, does not enter the Zener domainand functions satisfactorily when the base of said transistor Tr, isreversely biased immediately after setting. But in case the constant ais selected to be a value of nearly 1, two times or more of delaytimeswill be obtained with the same values of the timing resistor R andtiming capacitor C. Thus, in order to obtain a long delay time, in somecases it is more convenient to select the constant a to be a value ofnearly 1, rather than to double the size of the timing capacitor C.Then, in order to select the constant a to be a value of nearly 1, afirst stage transistor Tr, with a base-emitter withstand voltage higherthan the power supply voltage should be employed. Otherwise, a diode Dwith a withstand voltage higher than the power supply voltage should beconnected in series with both the positive electrode of the timingcapacitor C and the base of the first stage transistor Tr, as shown inFIG. 2, thereby to operate in a preferable condition regardless of thevalue of the constant a.

' Referring to FIG. 3, a circuit diagram of another embodiment of thepresent invention will be explained. The base of a third transistor Tr,is connected with the collector of the first stage transistor Tr, shownin the circuit of FIG. 1, and the collector of said transistor Tr, isconnected with the +8 power supply line and the emitter thereof isconnected with the base of the second stage transistor Tr In the circuitof FIG. 1, in case the power supply voltage is 12V and the excitingcurrent of the relay Y is I00 mA, the maximum value of the timingresistor R allowed to be employed is at most 2 through 3 megohms, sothat so long set time cannot be expected. On the other hand, in thecircuit of FIG. 3, the third transistor Tr, is additionarily employedand the DC. current amplification factor of the second stage transistorTr will be increased equivalently, thereby raising the base resistanceR, (timing resistance) of the first stage transistor Tr,.

In the circuit diagram of another embodiment in FIG. 4, a diode D isconnected between the first stage transistor Tr, and the timingcapacitor C, thereby enabling to function satisfactorily regardless ofthe value of the Y constant a.

By adding the third transistor Tr, as shown in FIGS. 3 and 4, in casethe relay Y requiring the exciting current of mA as mentioned above isused, the timing resistor R of 100 megohm can be employed, thus enablinga timer of dozens of minutes of set time to be realized.

the second stage transistor Tr rises to increase the loss of saidtransistor Tr In the circuit of the present embodiment, as the currentlimiting resistoris not connected with the collector or the emitter ofthe third transistor Tr (for the purpose of lowering the cost as much aspossible), there remains necessity that the resistance of the collectorresistor R of the first stage transistor Tr, should beproperlyselectednot to exceed the collector loss of the third transistor Tr Inthe present invention as mentioned above, the timing capacitor ischarged up in the direction for cutting off the transistor, then thevoltage is applied thereto in the direction for discharging the thuscharged charge to commence discharging and after a given time, saidtransistor will be made'conductive to determine a set time. Owing tosuch a construction, the present inventiori enables the constituentelements to be reduced as much as possible, allows conventionalsemiconductors of reasonable price to be employed, and allows the timerto be mass-produced, thus enablingthe cost to be lowered. Furtheraccording to the present invention, with a simple structure of thecircuit, a set time can be determined to be several seconds throughdozens of minutes and an excellent voltage characteristic andtemperature characteristic can be obtained. Moreover, as thepredetermined set time is not affected by the DC current amplificationfactor of the transistor, the operation of the relay and theopen-circuit voltage, fluctuation in quality of the products can bereduced and the yield can be improved. The present invention further hassome advantages that when it is not used for timer operation, the timercircuit and the load. are interrupted from the power supply, so that thewaste of electric power can be prevented and possible errorneousoperation owing to noises can be well prevented.

While there have been described and illustrated several specificembodiments of the invention, it will be clear that variations in thedetails of the embodiments specifically illustrated and described may bemade without departing from the true spirit and scope of the inventionas defined in the appended claim.

What is claimed is:

1. An off delay timing circuit for use in an automoa voltage divider anda timing capacitor coupled hereto; i

a setting switch connectible to'a power source and including set contactmeans actuable to a set condition for charging said timing capacitorthrough said voltage divider and forenergizing said load;

means connecting said timing capacitor to said first transistor forapplying the resulting charge voltage on said capacitor to said firsttransistor as a reverse bias;

a timing resistor and means connecting same to said timing capacitor andresponsive to switching of the setting switch from said set conditionfor discharging saidtiming capacitor gradually through the timingresistor to said power'source to define a timing interval;

circuit means-connected to said setting switch and load control meansand connectible to said load and source for isolating and preventingcurrent draw by the remainder of the timing circuit and said load fromsaid source other than when said setting switch is in its set conditionand .during said timing interval;

said set contact means including first, second and third set contacts,said circuit means including leads connectible from the second and thirdset contacts to said source and load respectively for energizing saidload from said source upon connection of the second and third setcontacts, and means connecting said first set contact to said voltagedivider and to the base of said second transistor for charging saidtiming capacitor from said source through said voltage divider andenergizing said second transistor from said source when said settingswitch is in its set condition, said setting switch further includingmeans for interconnectingsaid first, second and third set contacts whensaid setting switchis in its set position. 1 v

2. The circuit of claim 1, including conductor mean connecting saidthird set contact in series with said load control means and secondtransistor for allowing current flow therethrough when the settingswitch is in its set condition and also connecting said thirdset'contact in series with said first transistor, said third set contactalso being connected to said timing capacitor through said timingresistor, said load control means having a contact closable uponenergization thereof for energizing said third set contact from thepower source even when said setting switch is not in its set position 3.An off delay timing circuit for use in an automobile, comprising:

first and second transistors of the same polarity and means connectingsame in sequence for inverted operation with respect to each other;

load control means responsive to said second transistor for controllingenergization of a load;

a voltage divider and a timing capacitor coupled thereto;

a setting switch connectible to a power source and including set contactmeans actuable to a set condition for charging said timing capacitorthrough said voltage dividerand for energizing said load;

, means connecting said timing capacitor to said first transistor forapplying the resulting charge voltage on said capacitor to said firsttransistor as a reverse bias;

a timing resistor and means connectingsame'to said timing capacitor andresponsive to switching of the setting switch-from said set conditionfor discharging said timing capacitor gradually through the timingresistor to said power source to define a timing interval; 1

circuit means connected to said setting switch and load control meansand'connectible to' said load and source for isolating and preventingcurrent draw by'the remainder of the timing circuit and said load fromsaid source other than'when said settingswitch is in its set conditionand during said timing interval;

the setting switch including means defining a set condition for applyingenergizing potential from said source through said voltage divider tocharge said timing capacitor and to the base of the second transistorfor turning same on and for independently providing operating potentialfrom said source to the timing resistor, to the current carrying paths.of the first-and second transistors and to said load, said settingswitch further including means defining a resetconditionifor shortingthe base path through the second transistor to block conduction thereofand said setting switch further havng means defining-a neutral conditionfor eliminating both the set and reset connections therethrough. v

4. An off delay timing circuit for use in an automobile, comprising:

first and second transistors of the same polarity and means connectingsame in sequence for inverted transistor for applying the resultingcharge voltage on said capacitor to said first transistor as a reversebias; a v

a timing resistor and means connecting same to said timing capacitor andresponsive to switching of the setting switch from said set conditionfor discharging said timing capacitor gradually through the timingresistor to said power source to define a timing interval;

circuit means connected to said setting switch and load control meansand connectible to said load and source for isolating and preventingcurrent draw by the remainder of the timing circuit and said load fromsaid source other than when said setting switch is in its set conditionand during said timing interval;

means responsive to the set condition of said setting switch forconnecting said voltage divider-across said power source, said timingcapacitor being connected at one side to said voltage divider forcharging therefrom, said timing capacitor being connected at the otherside thereof to one end of said timing resistor and to the base of saidfirst transistor, means connecting the free end of said timing resistorfor energization by said power source during the set condition of saidsetting switch and during said time interval, whereby current flowthrough said timing resistor biases said first transistor conductiveduring the set condition of the setting sw-itch and the chargedcondition of said timing capacitor biases the base of the firsttransistor to nonconduction thereafter and to the end of the timinginterval.

5. The circuit of claim 4, including a diode interposed between saidtiming capacitor and the base of said first transistor for preventingreverse current flow through the base-emitter connection junction ofsaid first transistor.

6. An off delay timing circuit for use in anautomobile, comprising:

first and second transistors of the same polarity and means connectingsame in sequence for inverted operation with respect to each other;

load control means responsive to said second transistor'for controllingenergization of a load;

a voltage divider and a timing capacitor coupled thereto;

a setting switch connectible to a power source and including set contactmeans actuable to a set condition for charging said timing capacitorthrough said voltage divider and for energizing said load;

means connecting said timing capacitor to said first transistor forapplying the resulting charge voltage on said capacitor to said firsttransistor as a reverse bias; a timing resistor and means connectingsame to said timing capacitor and responsive to switching of the settingswitch from said set condition for discharging said timing capacitorgradually through the timing resistor to said power source to define atiming interval;

circuit means connected to said setting switch and load control meansand connectible to said load and source for isolating and preventingcurrent draw by the remainder of the timing circuit and said load fromsaid source other than when said setting switch is in its set conditionand during said timing interval;

a third transistor and means coupling same in sequence between first andsecond transistors for enhancing the DC current amplification factor ofthe second transistor, said third transistor being direct coupledthrough its base-emitter circuit between said first and secondtransistors and having the collector thereof connectible to the powersource, said timing resistor and timing capacitor being connected to thebase of said first transistor, whereby provision of said thirdtransistor allows raising of the value of said timing resistor and aconsequent increase in the timed interval.

1. An off delay timing circuit for use in an automobile, comprising:first and second transistors of the same polarity and means connectingsame in sequence for inverted operation with respect to each other; loadcontrol means responsive to said second transistor for controllingenergization of a load; a voltage divider and a timing capacitor coupledhereto; a setting switch connectible to a power source and including setcontact means actuable to a set condition for charging said timingcapacitor through said voltage divider and for energizing said load;means connecting said timing capacitor to said first transistor forapplying the resulting charge voltage on said capacitor to said firsttransistor as a reverse bias; a timing resistor and means connectingsame to said timing capacitor and responsive to switching of the settingswitch from said set condition for discharging said timing capacitorgradually through the timing resistor to said power source to define atiming interval; circuit means Connected to said setting switch and loadcontrol means and connectible to said load and source for isolating andpreventing current draw by the remainder of the timing circuit and saidload from said source other than when said setting switch is in its setcondition and during said timing interval; said set contact meansincluding first, second and third set contacts, said circuit meansincluding leads connectible from the second and third set contacts tosaid source and load respectively for energizing said load from saidsource upon connection of the second and third set contacts, and meansconnecting said first set contact to said voltage divider and to thebase of said second transistor for charging said timing capacitor fromsaid source through said voltage divider and energizing said secondtransistor from said source when said setting switch is in its setcondition, said setting switch further including means forinterconnecting said first, second and third set contacts when saidsetting switch is in its set position.
 2. The circuit of claim 1,including conductor means connecting said third set contact in serieswith said load control means and second transistor for allowing currentflow therethrough when the setting switch is in its set condition andalso connecting said third set contact in series with said firsttransistor, said third set contact also being connected to said timingcapacitor through said timing resistor, said load control means having acontact closable upon energization thereof for energizing said third setcontact from the power source even when said setting switch is not inits set position.
 3. An off delay timing circuit for use in anautomobile, comprising: first and second transistors of the samepolarity and means connecting same in sequence for inverted operationwith respect to each other; load control means responsive to said secondtransistor for controlling energization of a load; a voltage divider anda timing capacitor coupled thereto; a setting switch connectible to apower source and including set contact means actuable to a set conditionfor charging said timing capacitor through said voltage divider and forenergizing said load; means connecting said timing capacitor to saidfirst transistor for applying the resulting charge voltage on saidcapacitor to said first transistor as a reverse bias; a timing resistorand means connecting same to said timing capacitor and responsive toswitching of the setting switch from said set condition for dischargingsaid timing capacitor gradually through the timing resistor to saidpower source to define a timing interval; circuit means connected tosaid setting switch and load control means and connectible to said loadand source for isolating and preventing current draw by the remainder ofthe timing circuit and said load from said source other than when saidsetting switch is in its set condition and during said timing interval;the setting switch including means defining a set condition for applyingenergizing potential from said source through said voltage divider tocharge said timing capacitor and to the base of the second transistorfor turning same on and for independently providing operating potentialfrom said source to the timing resistor, to the current carrying pathsof the first and second transistors and to said load, said settingswitch further including means defining a reset condition for shortingthe base path through the second transistor to block conduction thereofand said setting switch further havng means defining a neutral conditionfor eliminating both the set and reset connections therethrough.
 4. Anoff delay timing circuit for use in an automobile, comprising: first andsecond transistors of the same polarity and means connecting same insequence for inverted operation with respect to each other; load controlmeans responsive to said second transistor for controlling energizationof a load; a voltAge divider and a timing capacitor coupled thereto; asetting switch connectible to a power source and including set contactmeans actuable to a set condition for charging said timing capacitorthrough said voltage divider and for energizing said load; meansconnecting said timing capacitor to said first transistor for applyingthe resulting charge voltage on said capacitor to said first transistoras a reverse bias; a timing resistor and means connecting same to saidtiming capacitor and responsive to switching of the setting switch fromsaid set condition for discharging said timing capacitor graduallythrough the timing resistor to said power source to define a timinginterval; circuit means connected to said setting switch and loadcontrol means and connectible to said load and source for isolating andpreventing current draw by the remainder of the timing circuit and saidload from said source other than when said setting switch is in its setcondition and during said timing interval; means responsive to the setcondition of said setting switch for connecting said voltage divideracross said power source, said timing capacitor being connected at oneside to said voltage divider for charging therefrom, said timingcapacitor being connected at the other side thereof to one end of saidtiming resistor and to the base of said first transistor, meansconnecting the free end of said timing resistor for energization by saidpower source during the set condition of said setting switch and duringsaid time interval, whereby current flow through said timing resistorbiases said first transistor conductive during the set condition of thesetting switch and the charged condition of said timing capacitor biasesthe base of the first transistor to nonconduction thereafter and to theend of the timing interval.
 5. The circuit of claim 4, including a diodeinterposed between said timing capacitor and the base of said firsttransistor for preventing reverse current flow through the base-emitterconnection junction of said first transistor.
 6. An off delay timingcircuit for use in an automobile, comprising: first and secondtransistors of the same polarity and means connecting same in sequencefor inverted operation with respect to each other; load control meansresponsive to said second transistor for controlling energization of aload; a voltage divider and a timing capacitor coupled thereto; asetting switch connectible to a power source and including set contactmeans actuable to a set condition for charging said timing capacitorthrough said voltage divider and for energizing said load; meansconnecting said timing capacitor to said first transistor for applyingthe resulting charge voltage on said capacitor to said first transistoras a reverse bias; a timing resistor and means connecting same to saidtiming capacitor and responsive to switching of the setting switch fromsaid set condition for discharging said timing capacitor graduallythrough the timing resistor to said power source to define a timinginterval; circuit means connected to said setting switch and loadcontrol means and connectible to said load and source for isolating andpreventing current draw by the remainder of the timing circuit and saidload from said source other than when said setting switch is in its setcondition and during said timing interval; a third transistor and meanscoupling same in sequence between first and second transistors forenhancing the DC current amplification factor of the second transistor,said third transistor being direct coupled through its base-emittercircuit between said first and second transistors and having thecollector thereof connectible to the power source, said timing resistorand timing capacitor being connected to the base of said firsttransistor, whereby provision of said third transistor allows raising ofthe value of said timing resistor and a consequent increase in the timedinterval.